Intel Names Its Data-Center Inference Chip: GPU D-Series, Starting With the D270 at 1.3 PFLOPS of FP8 in a 350-Watt Air-Cooled Card

Intel used the Open Compute Project Global Summit 2026 to give its data-center AI accelerator a real name. The chip code-named Crescent Island is now the Intel GPU D-Series, and its first product is the Intel GPU D270. The company also filled in the numbers it had been withholding all year.

The D270 is built on Intel's Xe3P architecture and is explicitly not a graphics card. Intel stripped out the display and ray-tracing units that would define a consumer GPU, spending the freed die area on compute, while keeping the media engine so the card can still handle video understanding and multimodal generation. The accelerator is organized as four compute slices, each with eight Xe3P cores, for 32 cores in total, alongside 256 vector engines and 256 XMX matrix units, 512KB of L1 cache per core and 32MB of unified L2 cache linking the slices.

Peak performance is 1.3 PFLOPS of FP8 with 1.5 TB/s of memory bandwidth inside a 350-watt thermal design. The card is a standard PCIe 5.0 add-in board with passive air cooling, which means it drops into conventional rack servers without liquid-cooling infrastructure. Intel-branded reference cards ship with 160GB of LPDDR5X, and ODM partners can build versions up to 480GB. Supported precisions span FP4, INT4, INT8, BF16, FP16, TF32 and FP64. Intel says a single D270 can serve a model of up to 300 billion parameters, and an eight-card system can handle more than a trillion — though the company has not published a reproducible test environment or any third-party benchmark, and parameter capacity is a memory statement, not a throughput one.

The most consequential design decision is memory. Where Nvidia and AMD put HBM stacks on their data-center accelerators, Intel is using LPDDR5X. That trades raw bandwidth for capacity and cost: 480GB against AMD's 432GB of HBM4 on the Instinct MI450X and Nvidia's 288GB of HBM4 on Vera Rubin, while HBM supply remains tight and expensive. For long-context inference and multi-tenant serving, where the working set is a model plus a large KV cache, capacity per dollar can matter more than peak bandwidth — a bet Intel is making openly.

Positioned against the rest of the PCIe accelerator market, 1.3 PFLOPS of FP8 at 350W is competitive: AMD's Radeon AI PRO R9700 lists 766 TFLOPS of FP8 at 300W, while Nvidia's RTX PRO 5500 Blackwell reaches 846 TFLOPS of FP8 at 600W. Intel is careful to say it is targeting a completely different envelope from Nvidia's Rubin parts, which push a theoretical 17.5 PFLOPS of FP8 per chip but require liquid cooling and kilowatt-class power budgets.

Intel also showed a new rack design built with partners on the OCP ORv3 standard, with some Xeon 6+ configurations scaling past 46,000 cores per rack at 133.45 kilowatts — a CPU-density pitch aimed squarely at agentic workloads, where many agents executing code and hitting databases consume cores rather than matrix math. On the software side, Intel is leaning on the common Xe software foundation it already maintains across integrated and discrete GPUs, and says it is working with OEMs, ODMs, neoclouds, independent software vendors and AI-native companies.

Delivery is the open question. Intel confirmed that it has begun shipping engineering samples to customers but has not disclosed pricing or a general availability date. The company is attempting this after the Data Center GPU Max family, code-named Ponte Vecchio, failed commercially and a string of silicon acquisitions never cohered into a coherent AI strategy. In a market short of every inference cycle, an air-cooled PCIe card with a large LPDDR5X pool is a pragmatic shape — but pragmatism is only half the problem. Whether the GPU D-Series gets traction will be decided by software maturity and by the benchmark numbers Intel has not yet published.