DeepX Tapes Out DX-M2 on Samsung 2nm: 80 TOPS at 5 Watts to Run 100-Billion-Parameter Models on Robots

South Korean chip startup DeepX said it completed the mask tape-out of its second-generation edge AI processor, DX-M2, in early November, handing final design data to Samsung Electronics' foundry division for production on SF2P, the company's second-generation 2-nanometer process. Photomask production follows the milestone, with first silicon expected in March 2027, customer evaluation samples in the second quarter of 2027, initial mass-production shipments in the fourth quarter and a full ramp in 2028. DeepX puts the total cost of taking the chip from design to manufacturable product at more than $100 million, a figure that covers performance validation and production engineering rather than a single tape-out.

The specifications are aimed squarely at machines rather than data centers. DX-M2 is designed to run generative models at roughly 5 watts, with an 80 TOPS neural processing unit and memory bandwidth raised to 150 gigabytes per second from 50 gigabytes per second on the previous generation. That is enough, the company says, to serve models with 20 billion to 100 billion total parameters at 3 billion to 20 billion active parameters, generating 10 to 30 tokens per second. Target workloads are large language models and vision-language models on robots, drones, industrial equipment and AI-capable PCs.

The most unusual piece is a memory-side bet. DeepX worked with Samsung's memory division on an LPDDR5x-PIM design that moves matrix-vector multiplication into the memory chips themselves, avoiding the cost of shuttling weights back and forth. On Llama 3.1 8B, DeepX says token generation improves by as much as 6.7 times at 2.7 times the power, or roughly double at unchanged power. Those are company figures without independent verification, and the compiler that would exploit the design has so far run only in simulation, with a version for real hardware still in development.

DeepX is not starting from zero. Its DX-M1, built on Samsung's 5nm process and in mass production since August 2025, had drawn 88 purchase orders worth about $13.3 million across 10 countries as of October 2026. Customers include Hyundai Motor Group's robotics lab for the DAL-e delivery robot and the MobED mobile platform, Baidu for roughly 40,000 units used in OCR cameras and data parsing, plus Lenovo, Advantech and AAEON. The company has guided to $40 million of revenue this year, more than double the $17 million target it set in 2025, after reporting 3.3 billion won of revenue and a 20.1 billion won operating loss in 2025.

Chief executive Kim Rok-won describes DeepX as a physical AI infrastructure company rather than a chip designer, which explains the routing. The pitch is not to displace Nvidia inside data centers but to remove the round trip to the cloud from the device: industrial customers care about energy, cost and latency, and many of them also have a hard boundary against sending factory data off site.

The DX-M2 received a CES 2027 Innovation Award in the AI category, following two awards at CES 2026, a useful signal for a company that still sells mostly to early industrial buyers.

What it means: the edge inference market is splitting into two camps, one pushing general-purpose accelerators with large software stacks and the other building narrow, low-power parts for specific physical workloads. DeepX sits in the second camp, and its wager is that a 5-watt part running a 100-billion-parameter model inside a robot will matter more than peak throughput in a rack. The risk is timing. First silicon arrives in 2027 and volume in 2028, by which point Nvidia's robotics line, Qualcomm and a crowd of Chinese edge vendors will have moved, and DeepX's memory-side computing advantage depends on a compiler that does not yet exist outside simulation.