Nvidia Finances a Multibillion-Dollar CoWoS Expansion at ASE's SPIL as TSMC Capacity Tightens

The bottleneck in AI chipmaking is no longer just the wafer fab. Reuters reported on Friday, citing an industry executive familiar with the matter, that Nvidia is providing billions of dollars in financing to expand CoWoS advanced packaging capacity at Siliconware Precision Industries, or SPIL, a subsidiary of Taiwan's ASE Technology. The funding will support new factory space and equipment, and the scale of the support has not previously been reported.

Nvidia did not respond to a request for comment, and ASE said it does not comment on market rumors involving its customers. The arrangement, if confirmed, would mark one of the largest known examples of a chip designer directly bankrolling its customer's packaging supply, a layer of manufacturing that until recently attracted little strategic attention.

"In the past, packaging was always something you never had to worry about," said Pat Gelsinger, former Intel CEO and now a partner at venture firm Playground Global. That has changed because modern AI processors are assembled from many chiplets: today's GPUs and CPUs routinely integrate 10 or more dies, sometimes as many as 20, and Gelsinger estimated that advanced packaging could eventually account for as much as half of a chip's total value.

The market is shifting accordingly. Research firm Yole Group predicts that in 2026 the advanced packaging market will overtake traditional packaging in size for the first time, with related capital spending approaching $28 billion. TSMC dominates the most sophisticated techniques, including chip-on-wafer-on-substrate, the technology that links processors and memory on a shared base and is used by Nvidia, AMD, Broadcom and most cloud companies building their own AI silicon. With TSMC's CoWoS capacity tight, designers are diversifying: Nvidia's reported SPIL deal is one result, and AMD has unveiled more than $10 billion in investments across Taiwan's semiconductor industry, including partnerships with ASE, SPIL and Powertech Technology.

Smaller suppliers are racing to fill the gap. Powertech, which works with AMD and Broadcom on panel-level packaging, plans to invest $400 million in an advanced packaging joint venture with Broadcom in Singapore targeting production in 2028. "The most important thing right now is capacity," said PTI senior vice president Jim Lin, noting customers are waiting for the company to ramp. TSMC itself is developing a chip-on-panel-on-substrate pilot line, while AMD CEO Lisa Su acknowledged in October that "we do need more capacity overall."

For the industry, the reported Nvidia-SPIL financing shows capex is now flowing to every layer of the AI hardware stack, not just foundry wafers and HBM memory. The company has previously been reported to have prepaid billions to Taiwan substrate makers alongside Intel and AMD, and this move extends that playbook one step further down the line: whoever controls packaging throughput increasingly controls how many GPUs can actually ship.