Tesla's Updated AI Roadmap Puts Dojo Back on the Table: a Chiplet D3 With Stacked HBM, Optimized for Space

Tesla has published an updated AI accelerator roadmap that quietly revives its canceled in-house training chip program — with a fundamentally different architecture — while rebranding the whole lineup around "Super Intelligence," or SI, a term Elon Musk has been pushing across his companies. The roadmap was reported by Tom's Hardware.

The most consequential shift concerns Dojo. Musk canceled the wafer-scale Dojo project in August 2025 and said in August 2026 that SpaceX and xAI would run their ground and space data centers entirely on Nvidia hardware, an apparent end to Tesla's flagship custom silicon effort. The new roadmap, however, lists a third-generation Dojo D3 training accelerator described as a chiplet design using 2.5D and 3D advanced packaging with stacked HBM memory — a break from the original Dojo D1, which relied on distributed on-chip SRAM and a system-on-wafer scheme that connected 25 D1 processors with 11 gigabytes of total SRAM.

The move to HBM is the tell. Modern models consume enormous memory for parameters, activations and intermediate states, and SRAM-based designs run out of headroom fast; HBM trades some latency and efficiency for capacity that scales. Tesla says D3 will be optimized for "space, training and scalability" — language that implies at least some variants need radiation tolerance for orbit. The company has not disclosed D3's compute, memory capacity, manufacturing process or schedule, and it remains unclear whether Tesla has abandoned wafer-level integration entirely or still stacks custom HBM on wafer-connected logic dies. The published materials suggest the more conventional chiplet route is likelier, since stacking HBM on wafer-level interconnect would compound design complexity, thermal difficulty and yield risk.

On the inference side, the roadmap's sixth-generation chip carries the new SI6 name and is projected to deliver roughly 80 times the compute of HW4 with nine times the memory. Based on how HW4's performance is commonly measured, that puts SI6 somewhere between about 17,280 and 46,080 TOPS — an estimate derived from the roadmap's ratio, not a Tesla-disclosed figure. Tesla has also begun applying the SI label retroactively to older chips, and the naming echoes Musk's recent confirmation that SpaceXAI will become SpaceXSI.

The strategic picture is an odd one: a company that outsourced its training compute to Nvidia 15 months ago now publishes a roadmap for training silicon aimed at orbit, where launch mass and radiation tolerance reshape every design trade-off. Roadmaps of this kind are statements of intent, not commitments — Tesla has canceled flagship chips before. But if D3 ships as drawn, it would mean Tesla's chip ambitions survived their cancellation by changing shape: smaller dies, bigger memory, and a destination where Nvidia's server racks do not easily follow.