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Qualcomm Validates HBC Memory Stacks That Push 133 TB/s Toward Its AI250 Accelerator

News · By: AIReport Admin · 1 hour ago · 👁 11
Qualcomm Validates HBC Memory Stacks That Push 133 TB/s Toward Its AI250 Accelerator

Qualcomm says its first High Bandwidth Compute stacks have passed hardware validation in San Diego. The design puts LPDDR memory on top of the compute die, cutting data travel from centimeters to micrometers. Early two-layer samples beat HBM4 by more than five times per watt, and the four-layer production version targets 133 TB/s for the AI250 accelerator, which samples in the first half of 2027. All figures are company-reported.

Qualcomm said on November 2 that its first-generation High Bandwidth Compute technology has completed hardware validation at its San Diego laboratory, covering full read-write operation and near-memory compute workloads. The milestone moves the company's attempt to replace HBM with stacked LPDDR from a paper architecture into a productization phase.

HBC flips the conventional memory hierarchy. Instead of stacking DRAM dies beside the processor over a silicon interposer, the way HBM does, Qualcomm stacks multiple layers of LPDDR directly on top of the compute die and connects them through silicon vias. A compute die sits at the bottom of the stack, performing near-memory compute and cutting data travel distances from centimeters to a few micrometers.

The validated early samples used a two-layer DRAM stack. Qualcomm says bandwidth per watt exceeded HBM4 by more than five times in testing, though it has not yet reached the six-fold target the company set for the technology. Production parts are expected to use a four-layer stack.

The first product to carry HBC will be the AI250 accelerator, which Qualcomm says will deliver an effective memory bandwidth of 133 TB/s — 18 times what the LPDDR5X-based AI200 achieves — and will sample in the first half of 2027. According to the company's data center roadmap published in June 2026, the follow-up AI300 will use a second-generation HBC with a design target of 54 times the AI200's effective bandwidth.

Qualcomm also disclosed that Samsung and SK Hynix have both proposed cooperating on HBC commercialization, while TSMC handles the integrated packaging process. The company stresses that all bandwidth and efficiency figures are its own design numbers rather than third-party benchmarks, and that real-world inference throughput will depend on capacity limits, packaging yield and software maturity — all of which remain to be proven at scale.

Sources: Qualcomm announcement; IT之家; MyDrivers.

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