Intel Wants a Piece of the Custom AI Chip Boom, and Its New Secret Weapon Is Marvell's Ex-Sales Chief

Intel has spent years watching Broadcom and Marvell collect the design fees on every custom AI accelerator installed in hyperscale data centers. Now it wants a cut of the manufacturing. Intel is accelerating its push into ASIC custom-chip foundry work, and CEO Lip-Bu Tan's key hire for the effort is Dean Jarnac, the former chief sales officer of Marvell, whom Intel appointed executive vice president and chief sales officer in August, with the transition completing in September.

Jarnac's resume is the point. He ran global sales, field applications engineering and sales operations at Marvell, a chip designer rather than a chipmaker, after senior sales leadership roles at Broadcom and AMD, giving him more than 30 years of semiconductor experience on the customer side of custom silicon. "Marvell designs chips, and so he knows pretty well how that whole process works when you work for a chip design company versus a company that designs and makes their own chips," analyst Jack Gold told wccftech.

The market he is being aimed at is crowded and lucrative. Google's TPU is designed with Broadcom, Marvell and MediaTek; Amazon's Trainium involves Marvell; Microsoft's Maia accelerator is a joint effort with OpenAI, Marvell and Broadcom; OpenAI recently unveiled its own custom accelerator, Jalapeno, with Broadcom; and Anthropic is reportedly developing an ASIC with Broadcom and Samsung. As inference demand explodes, custom accelerators are shifting from an alternative to a default for hyperscale operators.

Intel's own numbers show why it wants in. CFO David Zinsner said on the July earnings call that the company's ASIC business is approaching a $2 billion annualized run rate, up nearly threefold year over year, and could reach $4 billion in the not-too-distant future. Tan has described custom silicon as the most strategically significant growth engine for Intel Foundry and sized the overall AI custom-silicon market at more than $100 billion. Both figures are company statements, not independently audited.

The early customer list is real, if modest. In July, Intel announced a deal to design and manufacture Fortinet's SP6, a next-generation security processor for high-performance firewalls, the first publicly named foundry customer of the Tan era. Elon Musk confirmed in April that Tesla's Terafab AI chip project will use Intel's 14A process, making it the node's first heavyweight customer. Intel has also expanded an AI chip collaboration with Google.

Jarnac fits a pattern. Tan has deliberately placed outsiders in key roles, including former SK hynix CEO Shou-Chi Lee, who is driving Intel's memory efforts around technologies such as 3D-stacked DRAM, in a conscious effort to break the internal-promotion culture that critics blame for years of inertia. Intel is also leaning on packaging to differentiate, from EMIB-T silicon bridges to Foveros 3D die stacking, and industry reports suggest Nvidia may adopt Foveros as early as 2028.

The honest scoreboard: a security processor and a Tesla node commitment are encouraging but small against the scale of the ASIC gold rush. That race will be decided when a hyperscaler places a flagship accelerator in Intel's fabs as a second source to TSMC. Selling that second source is now Jarnac's job description.