Shenzhen Startup Reexen Raises 1 Billion Yuan in Six Months to Stack SRAM Compute on High-Bandwidth Flash

Reexen Technology, a Shenzhen-based compute-in-memory AI chip startup, says it has raised a cumulative 1 billion yuan - roughly $140 million - across multiple tranches of its Series B in the past six months, in one of the larger Chinese semiconductor financing runs of the quarter. The round assembled an unusually broad strategic lineup: Meituan's strategic investment arm, XPeng's Xinghang Capital, the industry fund linked to NAND maker YMTC, OmniVision, Yuanhe Puhua Capital, and most recently Zhiwei Capital and game giant miHoYo's strategic arm, with existing backers Yinghao Capital and Weihang Chuangxin doubling down.

The company, founded in 2018 and led by CEO Liu Hongjie - an ETH Zurich PhD who studied under neuromorphic pioneer Tobi Delbruck and has been named to MIT Technology Review's Innovators Under 35 - is betting that the memory hierarchy, not raw compute, is what will decide trillion-parameter model inference. Its core product architecture stacks SRAM compute-in-memory dies directly on top of high-bandwidth flash (HBF) or DRAM using TSV and hybrid bonding, under a design methodology it calls MPM - model, processor, memory co-design - summarized by the slogan "capacity first, then bandwidth, then compute."

The headline product in development, the ADA400 platform, targets more than 2TB of capacity and more than 4TB/s of bandwidth on a single card, aimed at serving models with a trillion or more parameters without clustering. On its current engineering validation platform, the company says DeepSeek-V4 decode runs at about 20 tokens per second on a single card plus four SSDs, and it claims the HBF-based design should lift per-card bandwidth and throughput by another 10x and whole-machine throughput by 100x. Those are company targets, not independently verified results.

The bet rides a real industry shift. At the Flash Memory Summit this year, SK hynix and SanDisk published the first OCP specification for high-bandwidth flash - stacks of 8 or 16 NAND dies reaching up to 512GB per stack with 0.4-3.0TB/s of bandwidth, connected over UCIe - positioning HBF as a new layer between HBM and SSD. Reexen says it is an Alpha partner in a leading vendor's HBF AI chip program, and that its existing compute-in-memory products are already shipping, with edge-side design wins at vivo, Honor and Lenovo and a place in a top US smart-glasses supply chain.

The investor list tells its own story: a food-delivery platform, an EV maker, a NAND-flash incumbent's fund, an image-sensor company and a game studio rarely co-invest, and their presence signals how far the demand for inference capacity now reaches beyond traditional data-center buyers. The MoE architecture is the hinge - total parameters are heading into the trillions while each token activates only a few experts, producing ever-larger and sparser KV caches that want a big, cheap, read-heavy memory tier. That is precisely the niche HBM fills poorly and SSDs fill slowly.

Proceeds will go toward tape-out of the HBF-and-SRAM fusion chip, the MPM software stack, and cloud-to-edge productization. Whether Reexen can hold its 10x-per-card target against the OCP-spec silicon coming from SK hynix and SanDisk is the real test; for now, the round is one of the clearest signals yet that China's chip investors see memory-bound inference, not another GPU, as the next contested layer.